{
  "ambient_K": 303.15,
  "pressure_Pa": 101325,
  "board_thickness_mm": 1.6,
  "heat_W": {"D1": 1.0, "Q1": 0.05, "R1": 0.45, "U1": 0.10, "board": 0.40},
  "fr4": {"k_W_mK": [16.9951, 16.9951, 0.283244], "rho_kg_m3": 2131.48, "cp_J_kgK": 559.764},
  "mc_layers_assumed": [
    {"name": "copper1", "thickness_mm": 0.035, "k_W_mK": 300.0},
    {"name": "fr4_insulation", "thickness_mm": 0.150, "k_W_mK": 0.27},
    {"name": "copper2", "thickness_mm": 0.035, "k_W_mK": 300.0},
    {"name": "bond_dielectric", "thickness_mm": 0.125, "k_W_mK": 1.0},
    {"name": "aluminum", "thickness_mm": 1.255, "k_W_mK": 205.0}
  ],
  "package_k_assumed_W_mK": {"D1": 10, "Q1": 1, "R1": 3, "U1": 1, "passives": 1, "connectors": 0.2},
  "surface_emissivity_assumed": 0.9,
  "original_horizontal_C": {"FR4": {"D1": 120.8, "Q1": 107.6, "R1": 109.2, "U1": 94.6}, "MC": {"D1": 97.1, "Q1": 98.0, "R1": 95.3, "U1": 94.5}},
  "notes": [
    "Source: current page of Simulation Results_240524.one, parsed as a table. The 2.0 in the last Power Total cell is interpreted as the grand total; individual loads sum to 2.0 W.",
    "FR4 conductivity visually transcribed from embedded image_10.png; OCR incorrectly reads normal conductivity as 0.282344.",
    "STEP thickness is 0.4103624 mm, corrected to documented fabrication thickness 1.6 mm.",
    "MC stack is a sensitivity-study assumption based on supplied LED board image 4.png; actual dielectric product and layer thickness require confirmation.",
    "Package conductivities are screening assumptions, not calibrated compact thermal models. Output package temperatures must not be called junction temperatures.",
    "Horizontal defaults to component-side up; the supplied report does not specify which side faces up unambiguously. Also run horizontal-down."
  ]
}